1. Field of the Invention
The present invention relates to a video camera for digital-computing a video signal.
2. Description of the Related Art
An example of data communication between a logical computing portion (hereinafter called a "microcomputer") and a signal processing portion in a conventional video camera (hereinafter called a "digital camera") for digital- computing a video signal will now be described with reference to FIGS. 1 and 2A to 2C.
FIG. 1 is a block diagram showing the structure of a conventional digital camera, and FIGS. 2A to 2C are timing charts showing a state of communication between an ordinary microcomputer and an interface.
Referring to FIG. 1, reference numeral 1 represents a lens, 2 represents an image sensing device for converting, into an electric signal, an image of an object projected by the lens 1, 3 represents an A/D converter for converting a video signal supplied from the image sensing device 2 into a digital signal, 4 represents a signal processing portion for computing a digital signal converted from the analog signal, 5 represents an interface portion for reading or writing data onto a data register included in the signal processing portion 4, 6 represents a microcomputer that receives data read by the interface portion 5 to process data in a predetermined manner or transmit data to be written to the interface portion 5, and 7 represents a D/A converter for converting computed video signal into an analog signal.
In the signal processing portion 4, reference numerals 411 to 41n represent writing registers for writing data received by the interface portion 5 from the microcomputer 6. Data to be stored in the registers 411 to 41n is data (for example, the gains of AGC signals, those of R, G and B signals for white balance and a value for determining a region for autofocusing process) required for operations to process the video signal in the signal processing portion 4. Reference numerals 421 to 42n represent reading registers for storing data in the signal processing portion 4 to transmit it to the microcomputer 6. Reference numeral 43 represents a status register for holding, for each register, a state whether data has been stored in each of the reading registers 421 to 42n or not. Reference numeral 44 represents an OR circuit for obtaining an interruption signal from load signals L1 to Ln of each reading register. Reference numeral 45 represents a data selector. Each of the aforesaid registers is a shift register which is capable of serially inputting/outputting data when it receives a clock. Reference numeral 46 represents a timing generator for generating a load signal for each register at an adequate timing during the signal process.
An image of an object projected by the lens 1 is converted into an electric signal by the image sensing device 2 and converted into a digital signal by the A/D converter 3 before it is transmitted to the signal processing portion 4. The signal processing portion 4 receives data from the microcomputer 6 through the interface portion 5, the data being required to process the digital signal supplied from the A/D converter 3. The microcomputer 6 receives data required to compute data from the signal processing portion 4 through the interface portion 5.
FIGS. 2A to 2C are charts showing timing of serial communication between the microcomputer 6 and the interface portion 5. The communication is performed through a clock line CLK, a writing data line DW, a reading data line DR, and a MODE line for selecting a data reading mode or data writing mode or address assignment mode, the aforesaid lines being shown in FIG. 1.
(Assignment of Address) PA0 (Writing of Data) PA0 (Reading of Status Data) PA0 (Reading of Data of Reading Register) PA0 (1) Assignment of the address of the status register 43, PA0 (2) Transference of data in the status register 43, PA0 (3) Assignment of the address of the reading register, and PA0 (4) Transference of data in the reading register. PA0 (1) Transference of data of predetermined address or that of addresses, PA0 (2) Assignment of the address of a reading register, and PA0 (3) Transference of data in reading register.
When mode information for assigning the address is transmitted from the microcomputer 6 to the interface portion 5 through the MODE line as shown in FIG. 2A, the interface portion 5 transmits a clock signal to the microcomputer 6 through the line CLK. The microcomputer 6 transmits address signals (A0 to A7) through the line DW in synchronization with the supplied clock. The interface portion 5 receives the address signal to set the address in an address register (omitted from illustration) in the interface portion 5.
If, for example, data writing mode information is transmitted from the microcomputer 6 through the line MODE as shown in FIG. 2B, the interface portion 5 transmits a clock signal to the microcomputer 6 through the line CLK similarly to the address assignment operation. The microcomputer 6 transmits writing data signals (D0 to D7) through the line DW in synchronization with the clock signal. The interface portion 5 receives the writing data. At this time, the interface portion 5 transmits a signal to any one of WCLK1 to WCLKn shown in FIG. 1 and corresponding to the register of the addresses in accordance with the address set previously and transfers writing data through a writing line WD in synchronization with the foregoing clock signal.
If data has been, in the signal processing portion 4 shown in FIG. 1, loaded into any one of the reading registers 421 to 42n through load signals L1 to Ln in response to load signals generated by the timing generator 46 at predetermined timing, the load signals pass through the OR circuit 44 and serve as interrupting signals for the microcomputer 6. The load signals as well as raise the bit in the status register 43 corresponding to the reading register, the bit being held until the data loaded into the reading register is read. The load signals, which have passed through the OR circuit 44, interrupt the microcomputer 6 through line IRQ shown in FIG. 1. The microcomputer 6 starts communication for obtaining information denoting the reading register into which data has been loaded.
The communication is performed in such a way that the address of the status register 43 is set by transmitting status register address to the interface portion 5 through the line DW at the timing shown in FIG. 2A. Then, the microcomputer 6, as shown in FIG. 2C, transmits information about the data reading mode to the interface portion 5 through the line MODE. When the interface portion 5 receives the foregoing mode information, it sets the data selector 45 so as to obtain an output from the status register 43 in accordance with the address supplied previously. Furthermore, the interface portion 5 transmits RCLK1 to RCLKn shown in FIG. 1 and corresponding to the status register to the signal processing portion 4. The status register 43 transfers data to the interface portion 5 through line RD in synchronization with the clock. When the interface portion 5 has received the data, it transmits a clock signal to the microcomputer 6 through the line CLK at the timing shown in FIG. 2C. Furthermore, in synchronization with this, the interface portion 5 transmits data obtained from the status register 43 trough the line DR.
When the microcomputer 6 receives data from the status register 43, it then discriminates the reading register in the signal processing portion 4 that has been brought to the loaded state. Then, the microcomputer 6 transmits the address of the loaded reading register to the interface portion 5 at the timing shown in FIG. 2A. The interface portion 5 sets the address therein. Then, the microcomputer 6 transmits data reading information to the interface portion 5 through the line MODE. The interface portion 5 sets the data selector 45 in accordance with the address set previously and transmits RCLK1 to RCLKn corresponding to the reading register in accordance with the address. The corresponding reading register transmits data in synchronization with the clock so as to be transferred to the interface portion 5 as RD. The interface portion 5 makes the data synchronize with the clock signal of the line CLK at the timing shown in FIG. 5 to transmit it to the microcomputer 6 through the line DR.
However, if data is transferred from the microcomputer 6 to the signal processing portion 4 in an effective period for the video signal, data which is different from the data that must be transferred is undesirably transmitted during data shifting in a case where the register in the signal processing portion 4, to which the data is transferred, is the shift register. If the register is a register which directly affects the waveform of the video signal, such as the white balance or AGC, noise appears in the image plane.
The conventional example requires the following four serial communications in the signal processing portion 4 from a moment the reading register is loaded to a moment the microcomputer 6 receives the data in the reading register:
Therefore, if the clock of the microcomputer is slow, a long time takes and the speed, at which a video signal is processed, is lowered. That is, problems rise in that response of an auto focus for adjusting the state of focusing of an optical system of a camera deteriorates or response of an automatic iris for adjusting the quantity of incidental light upon the optical system deteriorates.